P4C1024

The P4C1024/L is a 1,048,576-bit high speed CMOS static RAM organised as 128K x 8. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply.

Access times of 17 to 70 nanoseconds are available. CMOS is utilised to reduce power consumption to a low level.

The P4C1024/L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The low power version offers 2V data retention mode.

The P4C1024/L is packaged in a 32 pin 400 or 600 mil ceramic DIP and in a 32 pin ceramic SOJ.