3D Plus 3D4D32G72LB2758 DDR4 SDRAM Industrial Memory | APC Technology

3D4D32G72LB2758

3D4D32G72LB2758

3D Plus

1.2V, 32Gbit DDR4 SDRAM organised as 512Mb x64 (additional 8b for ECC)

The 3D4D32G72LB2758 is a 32Gbits high speed DDR4 SDRAM, organised as 512M x 64 bits and 8 bits additional for ECC. This synchronous device operates at a maximum transfer rate of up to 2400 MT/s (DDR4-2400), for an aggregate data rate of 153.6Gbps. The module is designed to comply with the key DDR4 SDRAM features including: (1) posted CAS by programmable additive latency, (2) On Die Termination, (3) programmable driver strength data, (4) clock rate of 1200MHs.

All the control and address inputs are synchronised with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK_t rising and CK_c falling). All I/Os are synchronised with a pair of bidirectional differential data strobes (DQS_t and DQS_c) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a RAS_n and CAS_n multiplexing style. The data bus inversion (DBI) reduces the power consumption and ground bounce. The 32Gbits DDR4 devices operate with two power supplies: 1.2V for VDD and VDDQ, and 2.5V for VPP wordline supply. This device is ideal for high-density memory.

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More Information
Attribute Value
Product Type DDR4 SDRAM
Data_Sheet

To request a datasheet, contact a member of our high-reliability team [email protected]

Configuration 512M x72
Package BGA 267
Temperature Range
  • -40°C to +85°C
  • -40°C to +95°C
  • -55°C to +125°C
Power Supply 1.2V
Features
  • Including decoupling and termination
  • Industrial up to Military temperature range
  • Organisation: 512M x 64 bits + 8b ECC
  • Max Clock rate available: 1200MHs
  • Max Transfer Rate 2400MT/s
  • VDD/VDDQ = 1.2V (1.14V to 1.26V)
  • VPP = 2.5V (2.375V to 2.75V)
  • Command/Address latency
  • Burst length (BL): 8 (BL8) and Burst Chop 4 (BC4) modes
  • Bi-directional Differential Data Strobe (DQS)
  • DLL aligns DQ and DQS transitions with CK
  • Commands entered on each positive CK transition
  • Data and data mask are referenced to both edges of a differential data strobe pair (Double data rate)
  • Programmable on-die termination (ODT)
  • Refresh: Self-refresh, Auto refresh and Partial array Self-refresh
  • ZQ calibration for DQ drive and ODT
  • Asynchronous RESET pin for Power-up initialisation and reset function
  • Package: 267 balls leaded FBGA
More Information
Attribute Value
Data Sheet Click here to view

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