3DLV21821VS2623
3DLV21821VS2623
3D Plus
21-Bit Channel Redundant LVDS Deserialiser
The 3DLV21821VS2623 Deserialiser with redundancy inside converts three LVDS data streams into 21 bits of CMOS/TTL data.
A phase-locked transmit clock is transmitted in parrallel with the data streams over a fourth LVDS link. Every clock cycle, 21 bits of input data are sampled and transmitted.
Nominal and Redundant LVDS output drivers can be shut off when Power-down is active. It is particularly well suited for use in high-reliability, high-speed data transmission applications, and easily achieved cross-coupling nominal and redundant system. The 3DLV21821VS2623 is packaged in a 56 pin SOP.
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| Attribute | Value |
|---|---|
| Features |
|
| Product Type | Serialiser/Deserialiser |
| Pin Assignment | SOP 56 - Pitch 0.50 mm |
| Temperature Range |
|
| Power Supply | 3.3 V power supply |
| Attribute | Value |
|---|---|
| Data Sheet | Click here to view |
