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Integrated line receivers. 8 word Tx FIFO.

ARINC 429 Data Management IC supporting 8 receive and 4 transmit buses.

3.3V operation. Integrated line receivers (2) and line driver. Programmable label recognition for 256 labels. 32 word Rx and Tx FIFOs. Three priority label buffers.

3.3V, 10Mbit/sec, EBR-1553 operation. BC, MT or RT. 32K x 16 RAM with optional error detection/correction, 16-bit parallel host interface.

3.3V operation. Integrated dual transceivers. 32K x 16 RAM, illegal command detection, data buffering, time tag, optional auto initialization, 16-bit parallel host interface.

Equivalent to HI-6120 with reduced package size and SPI host interface.

3.3V operation. Integrated dual transceivers. Single message processor.

3.3V operation. Integrated dual transceivers. Uses isolation transformer ratio 1:2.5 for transformer coupled mode.

3.3V, 1 Mbit Memory Module: 8-bit bus width, MRAM based on 128K

3.3V, 2 Mbit Memory Module: 16-bit bus width, MRAM based on 128K