3D Plus 3D3D8G32YB1741 DDR3 SDRAM Industrial Memory | APC Technology

3D3D8G32YB1741

3D3D8G32YB1741

3D Plus

1.35V, 8Gb DDR3 SDRAM organised as 256M x32

The 3D3D8G32WB1741 / 3D3D8G32YB1741 is a high speed stack multi-chip package integrated 4Gbits x 2 DDR3 SDRAM and fabricated with ultra high performance CMOS process containing 8 Gbits which is organised as 32Mbits x 8 banks by 32 bits.

This synchronous device achieves a high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features: (1) posted CAS by programmable additive latency, (2) On Die Termination (3) programmable driver strength data,(4) clock rate of 1600Mbps. All the control and address inputs are synchronised with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronised with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 8Gb DDR3 devices operates with a single power supply: 1.35V or 1.5V for VDD and VDDQ. This device is ideal for high density memory applications that require high speed transfer and compatibility with standard servers and networking equipment.

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More Information
Attribute Value
Product Type DDR3 SDRAM
Data_Sheet

To request a datasheet, contact a member of our high-reliability team [email protected]

Configuration 256M x32
Package FBGA 136
Temperature Range
  • -40°C to +85°C
  • -40°C to +95°C
  • -55°C to +125°C
Power Supply 1.35V or 1.5V
Features
  • JEDEC Standard ball-out
  • Combines two 4 Gb x 16 devices
  • VDD/VDDQ = 1.35V (1.283V to 1.45V) or 1.5V (1.425V to 1.575V)
  • Differential clock inputs (CK, /CK) operation
  • Posted CAS by programmable additive latency
  • Burst length: 8 (BL8) and Burst Chop 4 (BC) modes
  • Bi-directional Differential Data Strobe (DQS)
  • DLL aligns DQ and DQS transitions with CK
  • Commands entered on each positive CK transition
  • Data and data mask are referenced to both edges of a differential data strobe pair (Double data rate)
  • Programmable read burst : interleave or nibble sequential
  • Multi Purpose Register (MPR) for pre-defined pattern read out
  • Programmable on-die termination (ODT)
  • Refresh: Self-refresh, Auto Self-refresh and Partial array Self-refresh
  • High Temperature Self-Refresh rate enable
  • ZQ calibration for DQ drive and ODT
More Information
Attribute Value
Data Sheet Click here to view

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