P4C150
P4C150
Pyramid Semiconductor
4K (4Kx1) CMOS SRAM with separate I/O and chip clear
The P4C150 is a 4,096-bit ultra high-speed static RAM organised as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V ± 10%tolerance power supply.
Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds.
Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level.
The P4C150 is available in 24-pin 300 mil DIP and SOIC packages providing excellent board level densities. The device is also available in a 28-pin LCC package as well as a 24-pin FLATPACK for military applications.
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| Attribute | Value |
|---|---|
| Key Features |
|
| Standard Military Drawing Number(s) | SMD 5962-88588 |
| TAA (ns) | 15/20/25/35 |
| DIP | 24 |
| LCC | 28 |
| Qualified To | MIL-STD-883 |
| Size | 4K |
| Attribute | Value |
|---|---|
| Data Sheet | Click here to view |
